Recently during the Linley Fall Processor Conference, Intel stuns everyone with its 10nm Atom Next-gen which is not comparable to Intel’s venerable ore chip series. This has ultra power architecture and powers countless ULP devices.
A few examples of ULP devices are the Internet of Things devices, tablets, and micro-servers. All these segments are still under Intel’s bastion provided that AMD cannot compete in these given areas.
Intel’s move to the 10nm Atom Tremont architecture begins with a focus on single-threaded performance but also brings other major improvements to bear, like the addition of L3 cache, a first for Atom, new instruction support, and enhanced security.
Intel claims that the culmination of these efforts has resulted in up to 30% more IPC for Tremnt compared to the previous Goldmont architecture. But somehow Intel is still remaining tight-lipped on the device’s clock speed. Therefore, the increased IPC may give it room to accommodate lower frequencies that come as a byproduct of the new and yet to be refined 10nm process, much similar to the Ice Lake Processor.
This process strangely allowed Intel to diversify into two different architectures to bank on the efficiency and low power of the technology’s core. Blending with Sunny Cove core’s high performance, these two can together create a combination similar to Intel’s hybridx86 architecture.
Tremont which is behind other traditional form processors lies behind the architectural fusion of this as well.
By taking a closer look at the 10nm low-power processing cores, two most significant features have come into notice.
One is the Single Sequence Performance. Intel’s overarching design targets include a focus on single-threaded performance paired with improved power efficiency and performance density. The up-gradation of Tremont’s predictor to a core class performance equips the same accuracy level as the highly powered Sunny Cove counterparts. Intel has achieved this by adding a dual-stage prediction implementation and many suspects that they have used TAGE in one of its stages. The seamless architecture can decode a maximum of six out of order instructions and also sports a four-wide retire and allocation which is equipped with dual store pipelines.
The chips of this microarchitecture come in L2 cache and share four core modules that can carry up to 4.5MB.
The second thing is the appearance. The new microarchitecture from Intel looks extremely impressive. Also, it shows a new performance level in a low powered space. But again, Intel hasn’t disclosed any information regarding the upcoming SoC’s. Other than Lakefield, Intel hasn’t dropped any clue as to when these next-gen devices will be available to the public.
Keeping this in mind, buyers should not expect the Tremont cores to be powered by the Goldmont architectures as of now as previously observed, an IPC upgrade is not always equivalent to some major upgrade in the overall performance. This is because the clock speed restrictions in the developing process result in the slowdown of the performance level.
Until the technology lands in the market, buyers can only keep their fingers crossed and wait for the final verdict.